Integrated circuit (IC) manufacturers produce dice (or die, the latter sometimes used to denote both the singular and the plural) on typically circular substrates referred to as wafers. A wafer may contain hundreds of individual rectangular or square dice, which are arranged in a two-dimensional array on the wafer. Dice-on-wafer, or “unsingulated” dice, must be tested to determine good from bad before the dice are singulated. Unsingulated die testing traditionally occurs by physically probing each die at its die pads, which allows a tester connected to the probe to determine good and bad dice. This type of probing is relatively slow and requires expensive mechanical mechanisms to step and position the probe accurately at each die location on the wafer. The probing step can damage the die pads which may interfere with the bonding process during IC packaging or assembly of bare dice into a multi-chip module (MCM). Also, as die sizes shrink, pads are positioned closer and closer together, making the job of probing more difficult and expensive.
Alternate conventional methods for testing unsingulated dice on wafers include: (1) designing each die to test itself using built-in-self-test (BIST) circuitry on each die and providing a way to enable each die BIST circuitry to test the die, (2) widening the scribe lanes between the dice to allow for test probe points or test circuitry, (3) processing an overlying layer of semiconductor material with test circuitry over the dice on wafers and providing via connections, from the overlying layer, to the pads of each die on the wafer and (4) providing a separate Joint Test Access Group (JTAG) interface for each die using widened scribe lines for all of the test access conductors.
Method 1 disadvantageously requires BIST circuitry on each die which takes up area, and the BIST circuitry may not be able to test the input/output (I/O) of the dice adequately. Method 2 disadvantageously reduces the number of dice that can be produced on a wafer since the widening of the scribe lanes takes up wafer area which could be used for additional dice. Method 3 disadvantageously requires additional wafer processing steps to form the overlying test connectivity layer on top of the dice on wafers, and also the overlying layer needs to be removed from the wafer after testing is complete. This overlying layer removal step is additive in the process and the underlying dice could be damaged during the removal step. Method 4 is likely to result in more JTAG interfaces than a tester can accommodate. The same holds true outside of the context of unsingulated dice on a wafer; packaged ICs and non-integrated circuits conventionally require separate testing and thus separate JTAG interfaces.
Ideally, only good dice are singulated and packaged into ICs. The cost of packaging dice is expensive, and therefore the packaging of bad dice increases the manufacturing cost of the IC vendor and results in a higher cost to the consumer.